`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2023/08/22 22:43:38
// Design Name: 
// Module Name: cpu_exmem
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module cpu_exmem(
    input wire rst,
    input wire clk,
    input wire[4:0] ex_wd,
    input wire ex_wreg,
    input wire[31:0] ex_wdata,
    output reg[4:0] mem_wd,
    output reg mem_wreg,
    output reg[31:0] mem_wdata,
    input wire ex_rmem,
    output reg mem_rmem,
    input wire ex_wmem,
    output reg mem_wmem,
    input wire[31:0] ex_wmem_data,
    output reg[31:0] mem_wmem_data
    );
    
    always @ (posedge clk) begin
        if (rst == 1'b1) begin
            mem_wd <= 5'b0;
            mem_wreg <= 1'b0;
            mem_wdata <= 32'h0;
            mem_rmem <= 1'b0;
            mem_wmem <= 1'b0;
            mem_wmem_data <= 32'b0;
        end else begin
            mem_wd <= ex_wd;
            mem_wreg <= ex_wreg;
            mem_wdata <= ex_wdata;
            mem_rmem <= ex_rmem;
            mem_wmem <= ex_wmem;
            mem_wmem_data <= ex_wmem_data;
        end
    end
    
endmodule
